Oversees definition, design, verification co-definition, and documentation for SerDes development.
Leads architecture design, rtl development, constraints, synthesis, timing analysis, verification, documentation, and support for SerDes designs.
Knowledge of all aspects of the process flow from high-level RTL design to synthesis, RTL/ netlist audits (using tools such as Spyglass), Formal verification, constraints development and analysis in the context of synthesis and over all use in PrimeTime, Timing model generation (ETM/ .db).
In depth knowledge of Serdes specifications, integration and design. First contact for any customer questions.Responsible for Database and tools management.
In depth knowledge of Serdes architecture and protocols a must. RTL, Verification, Synthesis flows, lint and CDC analysis (spyglass), constraints development and timing model creation (primetime).
Knowledge of spyglass, VC spyglass, design compiler and primetime.
QUALIFICATIONS
Bachelors in Electrical/Electronics engineering with at least 15 years or more experience in SerDes architecture and digital design
In depth knowledge of VLSI design tools for lint, CDC, synthesis, Verification, DFT insertion, timing analysis and scripting languages.
