IC Verification Engineer
Date posted - Aug 30, 2024
JOB DESCRIPTION
Architect and Develop scalable and reusable Testbench Environment using the framework of Verification Methodologies.
Develop Test plans for all features of the design, conduct reviews, Write Functional coverage for these features.
Build pseudo-random tests to Verify the design and achieve full Functional coverage and stability of Regressions
Debug Regression failures, analyze Functional Coverage gaps and improve Tests to cover the gaps
Work with other members of the team, guide/mentor junior team members
Lead the documentation of Verification Strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
Come up with strategies to improve Verification quality and Efficiency
Bachelors degree in Electrical Engineering or related degree and 12+ years related experience or Masters degree in Electrical Engineering or related degree and 10+ years related experience
Decade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
Very proficient in System Verilog and Verification Methodologies like UVM
Good debug skills in analyzing regression failures and understanding of complex designs
A good understanding of a layered complex protocols like PCI Express or other multi-layered protocol
Work with the team and mentor junior engineers