Principal/Sr Principal Package Design Engineer
Date posted - May 13, 2022
JOB DESCRIPTION
Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
· 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
· Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
· Schedule, prioritize, & track your work across 2+ projects simultaneously
· General flip-chip BGA package design & engineering
BSEE or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
· MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
· Knowledge of package-level signal integrity and power integrity, to apply to package designs
· Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
· Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
· Self-management and organization skills