Staff/Principal ASIC/RTL Design Engineer
Date posted - May 02, 2022
JOB DESCRIPTION
Fortune 500 Client is seeking a highly qualified candidate as a Senior Logic Design Engineer for Packet Processing
In this position, you would be joining an innovative team that designs and builds the hardware, software and networking technologies that power the infrastructure of the leading data centers in the world.
Our organization works on all levels of ASIC development, spanning high-level architecture, to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team as a Senior Logic Design Engineer.
As a Senior Logic Design Engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant RTL to implement components of complex networking ASICs.
This is a senior role requiring participation through the full life-cycle of the program, from developing micro-architecture specifications, RTL implementation, unit verification, timing convergence, ECO implementation, debug analysis and reviews.
. B.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
. B.S. with 12 years of experience, or M.S. with 10 years of experience in digital design on multiple networking ASICs. .
. 5+ years of experience in Verilog based RTL design or verification, in deep submicron technologies..
. Familiarity with Ethernet and other networking protocols. .
. Familiarity with packet processing concepts. .
. Extensive experience with Ethernet, TCP/IP, MPLS, tunneling and other networking protocols. .
. Extensive experience with packet processing architectures packet parsing, ACLs, metering, policing, etc. .
. Experience achieving timing closure on high performance ASICs, in deep submicron technologies. .
. Experience with low power design techniques, power estimation methods, clock domain crossing techniques. .
. Experience with scripting languages, such as Python or Perl.