Staff/Principal ASIC Implementation Engineer - Timing, Syntheses, Logic Equivalency
Date posted - Jan 15, 2022
JOB DESCRIPTIONAs a member of the team at PLP division in Broadcom Inc, you will be responsible for understanding design timing intent, constraints development, synthesis, static timing analysis and ensuring design meets power, area and performance goals. In this role you will: Work closely with the design team for constraint development, synthesis and logic equivalency and with the physical design team for static timing analysis. Participate in block and chip level implementation, developing and executing synthesis, STA and power analysis flows. Work with many cross functional team members, and will have the opportunity to enhance design methodology.
QUALIFICATIONSRequirements: - Typically requires a BSEE/CE degree and 8 years of experience or MSEE/CE degree and 6 years of experience - Hands-on experience in timing constraint development and Synthesis using industry standard tools is a must - Strong expertise in flow and infrastructure development for synthesis of block and SOC level is required - Hands-on experience with industry standard logic equivalency tools is a must - Hands-on experience with Static Timing Analysis (STA) tools is a must, preferably at the SOC level - Good expertise in TCL and Perl scripting - Should be knowledgeable in physical design activities to interact with the physical design team - Strong collaboration with RTL design team, understanding of Verilog/VHDL - Good understanding of DFT flow is a plus - Strong analytical and problem solving skills - Strong verbal and written communication skills
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